1. Technical Field
The present invention relates generally to digital circuits, and more particularly to the generation of synchronized digital signals of complementary state.
2. Description of the Related Art
The pervasiveness of digital systems in computers and communication systems necessitates quality digital signal synchronization whether it be within an integrated circuit processor, on bus systems of a personal computer or server, or in the transmission or receiver systems of wireless devices. The significance of synchronization has increased dramatically as the frequencies of the digital signals have increased into the GHz range. A key aspect of such synchronization is the management of skew within signals, such as a system clock signal, not only in the distribution process but in circuit implementations of the signals. A particular example of the skew problem arises when complementary forms of a digital signal are necessary, namely, the signal and its complement with minimum relative skew there between.
The generation of two complementary signals that are 180 degrees apart in phase from a single phase input signal has been approached through different techniques in the prior art. One common technique employs multiple strings of inverters driving matched capacitors necessitating designs with precise gate level matching of the field of transistors and matching of the capacitive devices to minimize signal skew between the complementary version of the signal. This technique is very susceptible to manufacturing process variations normally associated with the fabrication of integrated circuit devices, which variations are tending to increase as device sizes shrink. Another common technique employs the use of XOR gates, but again requires gate level matching of differing integrated circuit devices and is susceptible to asymmetry with respect to the supply voltage and ground inputs, as well as the aforementioned sensitivity to fabrication process variations. A further technique is described in U.S. Pat. No. 6,466,074, wherein slew control is carefully managed by the sizing and placement of differing integrated circuit devices. Other practices of slew control potentially applicable to skew management and the generation of complimentary signals are described in U.S. Pat. Nos. 4,456,837, 4,987,324 and 5,568,081. Another technique for generating complementary signals is described in U.S. Pat. No. 6,384,658, where again device and layout matching are practiced to split a clock signal in pursuit of generating an inverted clock signal. The use of logic gates to generate complementary output signals of a digital input are described in U.S. Pat. No. 5,047,659, but again the practice of using gate delays necessitates matching of differing devices and thereby becomes susceptible to manufacturing process variations.
The prevalence of using signals and their complements in digital circuits, most often clocking, at the GHz frequencies now commonly encountered, necessitates a structurally simple circuit configuration which takes a digital input signal and generates a complimentary pair of signals with minimum skew, and which is composed of active integrated circuit devices which can be manufactured with relatively matching characteristics with provisions for adjustability if the circumstances of the application so necessitate.